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Models / Reference Design

Verilog Model

Verilog behavioral models are provided by Macronix for each memory product. The high level language model contains device functionality descriptions and datasheet timing constraints. This allows users to emulate the Macronix device in their system during early development. Verilog models can be simulated using industry-standard digital circuit simulators (e.g. NC-Verilog, VCS) and allow digital circuit simulation and timing verification in the user's application system.


IBIS (Input/Output Buffer Information Specification) behavioral models describe the electrical characteristics of the I/O buffers and packaging. The IBIS model includes current vs. voltage drive characteristics and rise/fall times, as well as the values of certain parasitic components across datasheet temperature and voltage ranges. IBIS models are industry-standard format that are used to perform board level signal integrity simulations and timing analysis.