Process Design List

• Simulation models (Hspice, Spectre)
• Monte Carlo Statistical model
• Layout design rule
• Electrical rule
• ESD guideline
• PCM data
• Process characterization report

Physical Verification Files

• DRC/ANT/ESD/LVS: Calibre
• RC Extraction: Star-RC, Calibre-xRC, LPE

Layout Technology Files

• Pcell: Cadence IC5x & IC6x
• Mcell: Synopsys Laker2 & 3

Standard Cell

• 7, 9, and 12 track libraries are available for 0.18μm, using 5.0V & 1.8V technology
• Multiple drive strengths
• Applicable for 3-6 metal layers
• Precise timing and physical models for Cadence and Synopsys EDA suite

IO Cell

• Pure 5V or 5/1.8V mixed voltage
• Inline and core limited IO
• Applicable for 3-6 metal layers
• User configurable GPIO for different drive strengths and features
• 2-40Mhz Oscillator IO cell

​​​​​​​​SRAM Complier

• In-house developed SRAM complier for 0.18μm, which use 5V & 1.8V process with bit-cell area 10μm2 and 4μm2 respectively
• Hard macros available for other platforms

Embedded NVM

• Macros (0.25~8Mb) for 0.11um eOTP process
• 0.18um eOTP/eMTP/eFlash (in development)

Supporting Services

• In house ESD pre-tape out review
• Customize library characterization
• Physical implementation consultation